The design window for a modern memory controller has been shrinking significantly due to both the increasing interconnect speed and increasing variation seen in high volume manufacturing of the silicon, package, dual inline memory module (DIMM), and motherboard. Current designs use DLLs (delayed lock loops) to center the address, command and data signals in the middle of the eye and recover some of this lost timing margin. The term “eye” generally refers to the particular characteristic appearance of the data signal waveforms. This has led to an increase in circuit area and complexity to tackle the problem as well as limiting the frequency scaling possible with double data rate (DDR) technology. Currently, some memory controllers test for DLL settings using software controls with a limited number of samples.